/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
 * Copyright (C) STMicroelectronics 2024 - All Rights Reserved
 * Author: Clément Le Goffic <clement.legoffic@foss.st.com> for STMicroelectronics.
 */

#ifndef _DT_BINDINGS_STM32MP25_HDP_H
#define _DT_BINDINGS_STM32MP25_HDP_H

/* define a macro for each function a HDP pin can transmit */
#define HDP0_PWR_PWRWAKE_SYS			     "0"
#define HDP0_CPU2_SLEEP_DEEP			     "1"
#define HDP0_BSEC_OUT_TST_SDR_UNLOCK_OR_DISABLE_SCAN "2"
#define HDP0_BSEC_OUT_NIDENM			     "3"
#define HDP0_BSEC_OUT_NIDENA			     "4"
#define HDP0_CPU2_STATE_0			     "5"
#define HDP0_RCC_PWRDS_SYS			     "6"
#define HDP0_GPU_DBG7				     "7"
#define HDP0_DDRSS_CSYSREQ_DDRC			     "8"
#define HDP0_DDRSS_DFI_PHYUPD_REQ		     "9"
#define HDP0_CPU3_SLEEP_DEEP			     "10"
#define HDP0_D2_GBL_PER_CLK_BUS_REQ		     "11"
#define HDP0_PCIE_USB_CXPL_DEBUG_INFO_EI_0	     "12"
#define HDP0_PCIE_USB_CXPL_DEBUG_INFO_EI_8	     "13"
#define HDP0_D3_STATE_0				     "14"
#define HDP0_GPOVAL_0				     "15"

#define HDP1_PWR_PWRWAKE_CPU2			     "0"
#define HDP1_CPU2_HALTED			     "1"
#define HDP1_CPU2_STATE_1			     "2"
#define HDP1_BSEC_OUT_DBGENM			     "3"
#define HDP1_BSEC_OUT_DBGENA			     "4"
#define HDP1_EXTI1_SYS_WAKEUP			     "5"
#define HDP1_RCC_PWRDS_CPU2			     "6"
#define HDP1_GPU_DBG6				     "7"
#define HDP1_DDRSS_CSYSACK_DDRC			     "8"
#define HDP1_DDRSS_DFI_PHYMSTR_REQ		     "9"
#define HDP1_CPU3_HALTED			     "10"
#define HDP1_D2_GBL_PER_DMA_REQ			     "11"
#define HDP1_PCIE_USB_CXPL_DEBUG_INFO_EI_1	     "12"
#define HDP1_PCIE_USB_CXPL_DEBUG_INFO_EI_9	     "13"
#define HDP1_D3_STATE_1				     "14"
#define HDP1_GPOVAL_1				     "15"

#define HDP2_PWR_PWRWAKE_CPU1			     "0"
#define HDP2_CPU2_RXEV				     "1"
#define HDP2_CPU1_NPMUIRQ1			     "2"
#define HDP2_CPU1_NFIQOUT1			     "3"
#define HDP2_BSEC_OUT_SHDBGEN			     "4"
#define HDP2_EXTI1_CPU2_WAKEUP			     "5"
#define HDP2_RCC_PWRDS_CPU1			     "6"
#define HDP2_GPU_DBG5				     "7"
#define HDP2_DDRSS_CACTIVE_DDRC			     "8"
#define HDP2_DDRSS_DFI_LP_REQ			     "9"
#define HDP2_CPU3_RXEV				     "10"
#define HDP2_HPDMA1_CLK_BUS_REQ			     "11"
#define HDP2_PCIE_USB_CXPL_DEBUG_INFO_EI_2	     "12"
#define HDP2_PCIE_USB_CXPL_DEBUG_INFO_EI_10	     "13"
#define HDP2_D3_STATE_2				     "14"
#define HDP2_GPOVAL_2				     "15"

#define HDP3_PWR_SEL_VTH_VDDCPU			     "0"
#define HDP3_CPU2_TXEV				     "1"
#define HDP3_CPU1_NPMUIRQ0			     "2"
#define HDP3_CPU1_NFIQOUT0			     "3"
#define HDP3_BSEC_OUT_DDBGEN			     "4"
#define HDP3_EXTI1_CPU1_WAKEUP			     "5"
#define HDP3_CPU3_STATE_0			     "6"
#define HDP3_GPU_DBG4				     "7"
#define HDP3_DDRSS_MCDCG_EN			     "8"
#define HDP3_DDRSS_DFI_FREQ_0			     "9"
#define HDP3_CPU3_TXEV				     "10"
#define HDP3_HPDMA2_CLK_BUS_REQ			     "11"
#define HDP3_PCIE_USB_CXPL_DEBUG_INFO_EI_3	     "12"
#define HDP3_PCIE_USB_CXPL_DEBUG_INFO_EI_11	     "13"
#define HDP3_D1_STATE_0				     "14"
#define HDP3_GPOVAL_3				     "15"

#define HDP4_PWR_SEL_VTH_VDDCORE		     "0"
#define HDP4_CPU2_SLEEPING			     "1"
#define HDP4_CPU1_EVENTO			     "2"
#define HDP4_CPU1_NIRQOUT1			     "3"
#define HDP4_BSEC_OUT_SPNIDENA			     "4"
#define HDP4_EXTI2_D3_WAKEUP			     "5"
#define HDP4_ETH1_OUT_PMT_INTR_O		     "6"
#define HDP4_GPU_DBG3				     "7"
#define HDP4_DDRSS_DPHYCG_EN			     "8"
#define HDP4_DDRSS_OBSP0			     "9"
#define HDP4_CPU3_SLEEPING			     "10"
#define HDP4_HPDMA3_CLK_BUS_REQ			     "11"
#define HDP4_PCIE_USB_CXPL_DEBUG_INFO_EI_4	     "12"
#define HDP4_PCIE_USB_CXPL_DEBUG_INFO_EI_12	     "13"
#define HDP4_D1_STATE_1				     "14"
#define HDP4_GPOVAL_4				     "15"

#define HDP5_CPU1_STANDBY_WFIL2			     "0"
#define HDP5_CPU1_NIRQOUT0			     "3"
#define HDP5_BSEC_OUT_SPIDENA			     "4"
#define HDP5_EXTI2_CPU3_WAKEUP			     "5"
#define HDP5_ETH1_OUT_LPI_INTR_O		     "6"
#define HDP5_GPU_DBG2				     "7"
#define HDP5_DDRCTRL_DFI_INIT_START		     "8"
#define HDP5_DDRSS_OBSP1			     "9"
#define HDP5_CPU3_STATE_1			     "10"
#define HDP5_D3_GBL_PER_CLK_BUS_REQ		     "11"
#define HDP5_PCIE_USB_CXPL_DEBUG_INFO_EI_5	     "12"
#define HDP5_PCIE_USB_CXPL_DEBUG_INFO_EI_13	     "13"
#define HDP5_D1_STATE_2				     "14"
#define HDP5_GPOVAL_5				     "15"

#define HDP6_CPU1_STANDBY_WFI1			     "0"
#define HDP6_CPU1_STANDBY_WFE1			     "1"
#define HDP6_CPU1_HALTED1			     "2"
#define HDP6_CPU1_NAXIERRIRQ			     "3"
#define HDP6_BSEC_OUT_SPNIDENM			     "4"
#define HDP6_EXTI2_CPU2_WAKEUP			     "5"
#define HDP6_ETH2_OUT_PMT_INTR_O		     "6"
#define HDP6_GPU_DBG1				     "7"
#define HDP6_DDRSS_DFI_INIT_COMPLETE		     "8"
#define HDP6_DDRSS_OBSP2			     "9"
#define HDP6_D2_STATE_0				     "10"
#define HDP6_D3_GBL_PER_DMA_REQ			     "11"
#define HDP6_PCIE_USB_CXPL_DEBUG_INFO_EI_6	     "12"
#define HDP6_PCIE_USB_CXPL_DEBUG_INFO_EI_14	     "13"
#define HDP6_CPU1_STATE_0			     "14"
#define HDP6_GPOVAL_6				     "15"

#define HDP7_CPU1_STANDBY_WFI0			     "0"
#define HDP7_CPU1_STANDBY_WFE0			     "1"
#define HDP7_CPU1_HALTED0			     "2"
#define HDP7_BSEC_OUT_SPIDENM			     "4"
#define HDP7_EXTI2_CPU1__WAKEUP			     "5"
#define HDP7_ETH2_OUT_LPI_INTR_O		     "6"
#define HDP7_GPU_DBG0				     "7"
#define HDP7_DDRSS_DFI_CTRLUPD_REQ		     "8"
#define HDP7_DDRSS_OBSP3			     "9"
#define HDP7_D2_STATE_1				     "10"
#define HDP7_LPDMA1_CLK_BUS_REQ			     "11"
#define HDP7_PCIE_USB_CXPL_DEBUG_INFO_EI_7	     "12"
#define HDP7_PCIE_USB_CXPL_DEBUG_INFO_EI_15	     "13"
#define HDP7_CPU1_STATE_1			     "14"
#define HDP7_GPOVAL_7				     "15"

#endif /* _DT_BINDINGS_STM32MP25_HDP_H */
